Semiconductor memory devices have been continuously improved to increase operating speed as well as integration density. Synchronous memory devices designed to operate in synchronization with a clock provided outside the memory chips are conventionally used to increase the operating speed of semiconductor memory devices.
In typical synchronous memory devices, when data is outputted in synchronization with an external clock, a delay corresponding to an output data access time from clock (tAC) occurs so that a valid data window is reduced. As a result, an error occurs during high frequency operation. Therefore, a delay locked loop (DLL) circuit is used which generates a DLL clock by delaying an external clock by a predetermined time interval (tCK-tAC) in order to output data in exact synchronization with rising and falling edges of a clock. The DLL circuit generates a DLL clock in which a delay component inside a DRAM is adjusted with respect to an external clock in a locking state.
The locking state refers to a state in which a reference clock and a feedback clock are in a synchronized state. A conventional DLL circuit synchronizes a feedback clock with a reference clock by adjusting an initial delay time interval of a delay line upon initial operation.
FIG. 1 is a block diagram illustrating a configuration of a conventional data output control circuit.
As illustrated in FIG. 1, the conventional data output control circuit includes a DLL circuit 10 and an output enable signal generation unit 11. The DLL circuit 10 is configured to receive an external clock (CLK) and generate a DLL clock (DLLCLK). The output enable signal generation unit 11 is configured to generate an output enable signal OE for outputting data in synchronization with the DLL clock (DLLCLK).
This type of conventional data output control circuit continuously operates even when the DLL clock (DLLCLK) is not used, causing unnecessary current consumption.